полного тока от REFOUT, внешний буфер для заполнения.

ОУ, такие как AD811, AD8001, AD9631 и хорошие

выбор для превосходной динамические характеристики. В постоянного применения,

ОУ, такие как AD845 или AD797 могут оказаться более подходящими.

27

AD768

R

Полный пансион

1k Ω

IOUTA

LADCOM

IOUTB

75 Ω

24,9 Ω

R

P

20 Ω

A1

C

3

Я

Биполярные

R

BIP

1k Ω

REFOUT

Я

КСР

28

1

Рисунок 25. Биполярное ± 2,5 V Buffered выходное напряжение

ДИФФЕРЕНЦИАЛЬНАЯ КОНФИГУРАЦИИ OUTPUT

AC связи через трансформатор

Приложения, которые не требуют операции обычно полосы

трансформаторной связью пользоваться. Трансформатор связи дополняется

элементарных результатов AD768 нагрузке есть неотъемлемое преимущество

обеспечения электрической изоляции в то время как каких-либо дополнительных затрат

власти. Кроме того, правильно применить трансформатора не должны ухудшать

AD768 в выходной сигнал в отношении шума и искажений,

с трансформатором пассивного устройства. На рисунке 26

центра постучал выходной трансформатор, который обеспечивает необходимые постоянного тока

условиях нагрузки на выходах IOUTA и IOUTB на диске

± 0,5 V сигнал в 50 Ω нагрузки. В данной схеме, цент-

тер-постучал трансформатор импеданса 4 раза, что соответствует

соответствует коэффициенту 2. Таким образом, любая нагрузка, R

L

, Ссылается на

Первичная сторона умножается на коэффициент 4 (т.е., в данном случае

200 Ω). Для того чтобы избежать постоянного тока, впадающих в R-2R лестницы

КСР, средняя точка трансформатора должна быть кон-

подключены к LADCOM.

Для того, чтобы соответствовать минимальным соответствие напряжения

-1,2 V, максимальное дифференциальное сопротивление видел между

IOUTA и IOUTB не должна превышать 240 Ω. Обратите внимание, что

дифференциальное сопротивление состоит нагрузки R

L

, Ссылается на

первичной обмотке трансформатора параллельно с добавил раз-

альных сопротивления, R

DIFF

, Через два выхода. R

DIFF

как правило,

добавили в первичной обмотке трансформатора в соответствии с эффек-

Tive основным источником сопротивления нагрузки (т.е., в данном случае

200 Ω).

1

27

AD768

IOUTA

LADCOM

IOUTB

R

DIFF

200 Ω

T1

R

L

50 Ω

4:1 IMPEDANCE

RATIO

T1 = Mini-Circuits T4-6Т

28

Рисунок 26. Дифференциальный выход помощью трансформатора

DC связи через усилитель

Постоянного дифференциальных одного состава преобразование может быть легко AC-

complished по схеме показано на рисунке 27. Эта схема

будет затухать как постоянного и переменного тока в режиме источников ошибок из-за общего

на дифференциальный характер цепи. Таким образом, общий режим

шума (например, часы проходных), а также постоянного однополярного компенсировать ошибки

будут значительно сокращены. Кроме того, отличная температура ста-

Ити могут быть получены с помощью отслеживания температуры, тонкой пленки

резисторов R и R

REF

. Дизайн уравнений для цепи

при условии, что выход качели напряжения и может быть IREF

оптимизированы для конкретного приложения.

1

27

28

AD768

R *

IOUTA

LADCOM

IOUTB

R

REF

*

Я

REF

A1

R *

6

3

REFOUT

REFIN

V

OUT

V

OUT

= ± 4 I

REF

R

Где я

REF

=

2.5V

R

REF

V

OUT

± 2V

R = 200 Ω

R

REF

= 5 х 200 Ω

* OHMTEK TDP-1403

Рисунок 27. DC дифференциала к однополярных Преобразование

Питания и заземления СООБРАЖЕНИЯ

В системах, стремясь одновременно достичь высокой скорости и

высокая точность, реализации и строительство

Дизайн печатной платы схема часто, как это важно, как и схемы

конструкции. Собственные РФ методы должны быть использованы в выбор устройства,

размещения и маршрутизации, а также поставки в обход и заземления.

Поддержание низкого шума питания и земли имеет решающее значение

для получения оптимальных результатов от AD768. Рисунок 28 про-

Vides иллюстрации рекомендовал печатных плат

горизонтальной плоскости расположение, которое реализуется на AD768 оцен-

объема борту.

REV. B

-12 -

AD768

Рисунок 28. Печатные платы Ground Plane Макет

Рисунок 29. Printed Circuit Board Power Plane Layout

AD768

REV. B

-13 -

If properly implemented, ground planes can perform a host of

functions on high speed circuit boards: bypassing, shielding,

current transport, etc. In mixed signal design, the analog and

digital portions of the board should be distinct from each other,

with the analog ground plane confined to the areas covering

analog signal traces and the digital ground plane confined to

areas covering the digital interconnects.

All analog ground pins of the DAC, reference, and other analog

output components, should be tied directly to the analog ground

плоскости. The two ground planes should be connected by a path

1/4 to 1/2 inch wide underneath or within 1/2 inch of the DAC

as shown in Figure 28. Следует проявлять осторожность для того, чтобы

ground plane is uninterrupted over crucial signal paths. В

digital side, this includes the digital input lines running to the

DAC as well as any clock signals. On the analog side, this in-

cludes the DAC output signal, reference signal, and the supply

feeders.

The use of wide runs or planes in the routing of power lines is

also recommended. This serves the dual role of providing a low

series impedance power supply to the part, as well as, providing

some “free” capacitive decoupling to the appropriate ground

плоскости. Figure 29 illustrates the power plane layout used in the

AD768 evaluation board. The AD768 evaluation board uses a

four layer PC board which illustrates good layout practices as

которых говорилось выше.

It is essential that care be taken in the layout of signal and

power ground interconnects to avoid inducing extraneous volt-

age drops in the signal ground paths. It is recommended that all

connections be short, direct and as physically close to the pack-

age as possible, in order to minimize the sharing of conduction

paths between different currents. When runs exceed an inch in

length, some type of termination resistor should be considered.

The necessity and value of this resistor will be dependent upon

the logic family used.

For maximum ac performance, the DAC should be mounted

directly to the circuit board; sockets should be avoided since

they introduce unwanted capacitive coupling between adjacent

pins of the device.

POWER SUPPLY AND DECOUPLING

One of the most important external components associated with

high speed designs are the capacitors used to bypass the power

снабжения. Both selection and placement of these capacitors can

be critical and, to a large extent, dependent upon the specifics of

the system configuration. The dominant consideration in the

selection of bypass capacitors for the AD768 is the minimization

of the series resistance and inductance. Many capacitors will

begin to look inductive at 20 MHz and above. Ceramic and film

type capacitors generally feature lower series inductance than

tantalum or electrolytic types.

It is recommended that each power supply to the AD768 be de-

coupled by a 0.1 µ F capacitor located as close to the device pins

насколько это возможно. Surface-mount chip capacitors, by virtue of their

low parasitic inductance, are preferable to through-hole types.

Some series inductance between the DAC supply pins and the

power supply plane may help to provide additional filtering of

high frequency power supply noise. This inductance can be gen-

erated by using small ferrite beads.

A clean digital supply may be generated using the circuit shown

in Figure 30. The circuit consists of a differential LC filter with

separate power supply and return lines. Lower noise can be at-

tained using low ESR (Equivalent Series Resistance) type elec-

trolytic and tantalum capacitors.

Феррит

BEADS

100μF

ELECT.

10–20µF

Важными.

0.1μF

CER.

V

DD

DCOM

+5 V

DGND

+5 V

ЭЛЕКТРОСНАБЖЕНИЕ

TTL / CMOS

LOGIC

CIRCUITS

Рисунок 30. Differential LC Filter for Single +5 V

Применения

ПРИМЕНЕНИЕ

USING THE AD768 AS A MULTIPLYING DAC

The AD768 can be easily configured as a multiplying DAC

since I

REFIN

can be modulated from 1 mA to 7 mA. Приведи

ence amplifier sets the maximum multiplying bandwidth to 15

MHz, while any external capacitor to the NR node serves to

limit the bandwidth according to Figure 7. Я

REFIN

can be easily

modulated by properly scaling and summing into the IREFIN

node the modulating signal. Figure 31 demonstrates how the

modulating signal VMOD can be properly scaled and converted

to a current via R

REFMOD

such that its peak current does not ex-

ceed 3.0 mA. Figure 32 shows the AD768's typical distortion

versus the reference channel frequency.

6

3

AD768

R

REF

625 Ω

IREFIN

REFOUT

1μF

R

REFMOD

VMOD

VMOD

R

REFMOD

≤ ± 3.0mA

Figure 31. Typical Multiplying DAC Application

FREQUENCY – kHz

THD - дБ

-75

-40

250

2500

500

750

1000

1250

1500

1750

2000

2250

-70

-60

-55

-50

-45

-65

Я

REF

= 4.0+/–3 mA

Я

REF

= 4.0+/–2 mA

Я

REF

= 5.0+/–1 mA

Рисунок 32. Reference Channel Distortion vs. Frequency

REV. B

-14 -

AD768

AD768 IN MULTITONE TRANSMITTERS (FOR ADSL)

Communications applications frequently require aspects of

component performance that differ significantly from the

simple, single tone signals used in typical SNR and THD tests.

This is particularly true for spread-spectrum and frequency divi-

sion multiplexed (FDM) type signals, where information con-

tent is held in a number of small signal components spread

across the frequency band. In these applications, a combination

of wide dynamic range, good fine-scale linearity, and low inter-

modulation distortion is required. Unfortunately, a part's full

scale SNR and THD performance may not be a reliable indica-

tor of how it will perform in these multitone applications.

One example of an FDM communications system is the DMT

(discrete multitone) ADSL (Asymmetrical Digital Subscriber

Line) standard currently being considered by ANSI. Рисунок 33

shows a block diagram of a transmitter function.

The digital bits are used to QAM modulate each of approxi-

mately 200 discrete tones. An inverse FFT turns this modu-

lated frequency domain information into 512 time points at a

2.2 MSPS sample rate. These time points are then put through

an FIR interpolation filter to upsample (in this case to 4.4MSPS).

The bit stream is run through the AD768, which is followed by

a 4th order analog smoothing filter, then run to the line-driving

Схема

К

ПЕРЕДАТЧИК

BIT

STREAM

QAM

ENCODER

256

MODULATED

ЧАСТОТА

БИНС

512 TIME

ВОПРОСЫ

@ 2.2MSPS

1024 TIME

ВОПРОСЫ

@ 4.4MSPS

4TH ORDER

SMOOTHING

ФИЛЬТР

AD768

+BUFFER

2X

INTERPOLATOR

РПИ

INVERSE

БПФ

Рисунок 33. Typical DMT ADSL Transmit Chain

Figure 34a shows a frequency domain representation of a test

vector run through this system, while 34b shows the time do-

main representation. (Clearly the frequency domain picture is

more informative.) We wish to optimize the SINAD of each

4 kHz frequency band: this is a function of both noise

(wideband and quantization) and distortion (simple harmonic

and intermod).

OUTPUT – dB

FREQUENCY – Hz

0

-20

-40

-60

0

1.1M

-80

Figure 34a. Output Spectrum of ADSL Test Vector

TIME – 25µs/DIV

1,5

1,0

0,5

0

-0,5

-1,0

-1,5

OUTPUT – Volts

Figure 34b. Time Domain Output Signal of ADSL Test

Вектор

Table I and II show the available SNR and THD at the output

of the filter vs. frequency bin for the ADSL application.

AD768's combination of 16-bit dynamic range and 14-bit lin-

earity provides excellent performance for the DMT signal. Ее

fast input rate would support even faster rates of oversampling,

if one were interested in trading off digital filter complexity in

the interpolator for a simplified analog filter.

Table I. SNR vs. Frequency

Частота

SNR

151 kHz

70.1 dB

349 kHz

69.7 dB

500 кГц

69.4 dB

1 MHz

69.8 dB

Таблица II. THD от частоты

Частота

THD

160 кГц

–68.9 dBc

418 kHz

–64.0 dBc

640 kHz

–64.3 dBc

893 kHz

–63.8 dBc

AD768

REV. B

-15 -

AD768 EVALUATION BOARD

GENERAL DESCRIPTION

The AD768-EB is an evaluation board for the AD768 16-bit

30 Msps D/A converter. Careful attention to layout and circuit

design combined with analog and digital prototyping areas al-

lows the user to easily and effectively evaluate the AD768 in any

application where high resolution, high speed conversion is

требуется.

The digital inputs to the AD768-EB may be driven directly us-

ing the standard 40-pin IDC connector. An external clock is

Также требуется. These signals may be applied from a user’s

bench, or they can be generated from a circuit built on the

prototyping area. The analog outputs from the AD768-EB are

available on BNC connectors. These outputs may be configured

to use either resistors, op amps, or a transformer.

OPERATING PROCEDURE AND FUNCTIONAL

ОПИСАНИЕ

Власть

Power may be supplied to the AD768-EB by applying either

wires or banana plugs to the metal binding posts in cluded on the

печатной платы.

DGND. Digital Ground. The digital ground and the analog

ground are connected together underneath the AD768. Оптимальный

performance can be obtained with separate analog and digital

снабжения. For evaluation purposes, a single-supply which makes

a second analog and digital ground connection at the supply is

приемлемым.

+5D . The +5 V ( ± 5%) digital supply should be capable of sup-

plying 50 mA.

–5A. The –5 V ( ± 5%) analog supply should be capable of sup-

plying –75 mA.

AGND . Analog ground. The analog ground and the digital

ground are connected together underneath the AD768. Оптимальный

performance can be obtained with separate analog and digital

снабжения. For evaluation purposes, a single-supply which makes

a second analog and digital ground connection at the supply is

приемлемым.

– V

EE

. Negative analog supply; typically –5 V to –15 V. This

supply is used as the negative supply rail for the external op

усилителей. For the AD811 supplied with the AD768-EB, a supply

capable of supplying –20 mA (excluding external load require-

ments) is required.

+ V

КС

. Positive analog supply; typically +5 V to +15 V. This

supply is used as the positive supply rail for the external op

усилителей. For the AD811 supplied with the AD768-EB, a supply

capable of supplying +20 mA (excluding external load require-

ments) is required.

Аналоговые выходы

The analog output(s) from the AD768-EB are available on BNC

jacks “A” and “B.” The complementary current outputs from

the AD768 can be configured using either resistors, op amps, or

a transformer. Only the “A” portion of the AD768-EB is popu-

lated and shipped from the factory. The “B” side, or comple-

mentary output, may be populated by the user if so desired.

JP1. Buffered op amp output “A”. Jumper JP1 should be

installed if the buffered op amp output is desired. When JP1

is installed, JP2 and JP3 must be removed for proper

операции. The output, available on the “A” connector, has a

nominal voltage swing of 0 V to 2 V and is in-phase with the

digital input. This is the factory default setting.

JP 2. Bipolar 50 Ω transformer output. If jumper JP2 is in-

stalled, a transformer coupled output is available on the “A”

connector. When JP2 is installed, JP1 and JP3 must be re-

moved for proper operation. The transformer acts both as a

differential-to-single-ended converter and as an impedance

трансформатора. For proper operation, the transformer must be

terminated with a 50 Ω resistor . R2 must be replaced with

the 100 Ω resistor, R7. An additional 100 Ω resistor and the

transformer are included with the AD768-EB. Дополнительные

100 Ω resistor must be soldered into the appropriate position la-

beled “R3” and the transformer must be inserted into the

socket labeled “T1.” The nominal output voltage into a 50 Ω

load is 1 V pp centered on a common-mode voltage of 0 V.

JP3. Resistor output “A.” JP3 is used to connect the resistor

R2 to the “A” output. U2 should be removed from its socket.

Using a 24.9 Ω resistor for R2, the output is an unbuffered 0 V

to –0.5 V output that is out of phase with the digital input. Заново

sistor R2 may be replaced with other values, but careful atten-

tion to the recommended output compliance range should be

observed. When JP3 is installed, JP1 and JP2 must be re-

moved for proper operation .

JP4. Resistor output “B.” JP4 is used to connect the resistor

R3 to the “A” output. U3 should be removed from its socket.

The AD768-EB is shipped from the factory with resistor R3

замкнут на землю. A different value selected by the user can be

installed for R3 to generate an unbuffered output that is in-

phase with the digital input. Careful attention to the recom-

mended output compliance range should be observed when

selecting the value of R3. When JP4 is installed, JP5 must

be removed for proper operation .

JP5. Buffered op amp output “B.” Jumper JP5 should be in-

stalled if the buffered op amp output is desired. When JP5 is

installed, JP4 must be removed for proper operation .

The output is available on the “B” connector and has a nominal

voltage swing determined by the combination of resistors R3,

R9, and R10. This op amp is not provided with the AD768-EB.

Ссылка

Either the internal reference of the AD768 or an external refer-

ence may be selected on the AD768-EB. R12 is used to adjust

the full-scale output current of the AD768.

SW2. Internal/External reference select switch. When SW2 is

in position 1, the internal reference of the AD768 is selected.

When SW2 is in position 2, an external reference must be pro-

vided by the user.

Level-Shifting the Analog Output

Resistor sockets R8 and R6 can be populated with an appropri-

ately valued resistor to add dc offset current to an output which

uses the op amp configuration. As an example, to generate a

bipolar output signal, a 1.25 k Ω resistor installed into the “R8”

socket level-shifts the normally unipolar output by –1 V. The

factory defaults for R8 and R6 are open circuits.

REV. B

-16 -

AD768

Таблица III. Summary of Jumper Functionality

Установленная

Jumper Function

Перемычка

JP1

Buffered Output A

JP2

50 Ω Transformer Output

JP3 (STBY)

Unbuffered Output A

JP4

Unbuffered Output B

JP5

Buffered Output B

Таблица IV. AD768-EB Parts List

Ссылка

Value / Part Type Package

Qty /Bd

U1

AD768

28-Pin SOIC

1

U2

AD811

8-Pin DIP

1

T1

Mini-Circuits

Не установлен

1

T4–6T

A, B, CLOCK BNC JACKs,

Small, Vertical

3

Небольшой

JP1–5

Заголовок

2-Pin

5

SW1, 2

SPDT, Secme

0.1" × 0.3"

2

J1

40-Pin IDC

RA, Male,

1

Соединитель

w/ Latches

R1

500 Ω

1/4 W, 0.01%,

1

Vishay

R2

25 Ω

1/4 W, 0.01%,

1

Vishay

R3, R13–21, &

R23–29

Wire Jumpers

17

R5

500 Ω

1/4 W, 0.01%,

1

Vishay

R7

100 Ω

1/4 W, 0.01%,

1

Vishay

R11

51 Ω

1/8 W, 5%, Carbon 1

R12

10 k Ω Pot.

3266 W

1

C1–4

1 µ F Ceram. Cap. Освинцованный

4

C5–8, C10, 12,

0.1 µ F Chip Cap,

14, & C16–19

1206

11

C9, 11, 13, 15 22 µ F Tant. Cap., Teardrop,

4

25 V

0.1" Spacing

Часы входного

An external sample clock must be provided to either the BNC

connector labeled “CLOCK” or on Pin 33 of the IDC connec-

Tor. This clock must comply with the logic levels outlined in the

AD768 data sheet. The “CLOCK” input is terminated with a

removable 51 Ω resistor. The IDC connector clock connection

is unterminated.

SW1. Clock source select switch. When SW1 is in position 1, Pin

33 of the IDC connected is applied to the CLOCK input of the

AD768. When SW2 is in position 2, the “CLOCK” BNC connec-

tor is applied to the CLOCK input of the AD768.

Цифровой вход

The digital inputs of the AD768, DB0–DB15, are available via

J1, a 40-pin IDC connector. These inputs should comply with

the specifications given in the AD768 data sheet.

Layout Considerations

Figures 28 and 29 show the AD768-EB ground and power

plane layouts. Figures 35–38 show the schematic diagram, trace

routing, silk screening, and component layout for the AD768 4

layer evaluation board.

Separate ground and power planes have several advantages for

high speed layouts. (For further information outlining these

advantages, see the application note “Design and Layout of a

Video Graphics System for Reduced EMI” [E1309] available

from Analog Devices [(617) 461-3392].) A solid ground plane

can be used if the digital return current can be routed such that

it does not modulate the analog ground plane. If this is not pos-

sible, it may be necessary to split the ground plane in order to

force currents to flow in a controlled direction. Этот тип

grounding scheme is shown in the Figure 28. The ground plane

is separated into analog and digital planes that are joined

together under the AD768. In any case, the AD768 should be

treated as an analog component and a common ground connec-

tion should be made underneath the AD768 despite some pins

being labeled “digital” ground and some as “analog” ground.

A complete parts list for the AD768 evaluation board is given in

Таблица IV.

AD768

REV. B

–17–

IOUTA

NR

REFOUT

Северная Каролина

REFCOM

IREFIN

DB0 (LSB)

DB1

DB2

DB3

DB4

DB5

DB6

DB7

LADCOM

IOUTB

(–5V) V

EE

(+5V) V

DD

(MSB) DB15

DB14

DB13

DB12

DB11

DB10