Note that those samples within the pipeline A/D during any reference transition will be corrupted and should be discarded.
AD9240
REV.
–13–
DRIVING THE ANALOG INPUTS
ВВЕДЕНИЕ
The AD9240 has a highly flexible input structure allowing it to
interface with single-ended or differential input interface cir-
cuitry. The applications shown in sections Driving the Analog
Inputs and Reference Configurations, along with the informa-
tion presented in the Input and Reference Overview section of
this data sheet, give examples of both single-ended and differen-
tial operation. Refer to Tables I and II for a list of the different
possible input and reference configurations and their associated
figures in the data sheet.
The optimum mode of operation, analog input range and asso-
ciated interface circuitry will be determined by the particular
applications performance requirements as well as power supply
options. For example, a dc coupled single-ended input may be
appropriate for many data acquisition and imaging applications.
Also, many communication applications which require a dc
coupled input for proper demodulation can take advantage of
the excellent single-ended distortion performance of the AD9240.
The input span should be configured such that the system’s
performance objectives and the headroom requirements of the
driving op amp are simultaneously met.
Alternatively, the differential mode of operation provides the
best THD and SFDR performance over a wide frequency range.
A transformer coupled differential input should be considered
for the most demanding spectral-based applications which allow
ac coupling (eg, Direct IF to Digital Conversion). The dc-
coupled differential mode of operation also provides an enhance-
ment in distortion and noise performance at higher input spans.
Furthermore, it allows the AD9240 to be configured for a 5 V
span using op amps specified for +5 V or ± 5 V operation.
Single-ended operation requires that VINA be ac or dc coupled
to the input signal source while VINB of the AD9240 be biased
to the appropriate voltage corresponding to a midscale code
с переходной экономикой. Note that signal inversion may be easily accom-
plished by transposing VINA and VINB.
Differential operation requires that VINA and VINB be simulta-
neously driven with two equal signals that are in and out of
phase versions of the input signal. Differential operation of the
AD9240 offers the following benefits: (1) Signal swings are
smaller and therefore linearity requirements placed on the input
signal source may be easier to achieve, (2) Signal swings are
smaller and therefore may allow the use of op amps which
may otherwise have been constrained by headroom limitations,
(3) Differential operation minimizes even-order harmonic prod-
ucts and (4) Differential operation offers noise immunity based
on the device's common-mode rejection as shown in Figure 16.
As is typical of most CMOS devices, exceeding the supply limits
will turn on internal parasitic diodes resulting in transient cur-
rents within the device. Figure 31 shows a simple means of
clamping a dc coupled input with the addition of two series
resistors and two diodes. Note that a larger series resistor could
be used to limit the fault current through D1 and D2 but should be
evaluated since it can cause a degradation in overall performance.
AVDD
R
S1
30
V
КС
V
EE
D2
1N4148
D1
1N4148
R
S2
20
AD9240
Рисунок 31. Simple Clamping Circuit
DIFFERENTIAL MODE OF OPERATION
Since not all applications have a signal preconditioned for
differential operation, there is often a need to perform a
single-ended-to-differential conversion. A single-ended-to-
differential conversion can be realized with an RF transformer
or a dual op amp differential driver. The optimum method
depends on whether the application requires the input signal to
be ac or dc coupled to AD9240.
AC Coupling via an RF Transformer
An RF transformer with a center tap can be used to generate
differential inputs for the AD9240. It provides all of the benefits
of operating the ADC in the differential mode while contribut-
ing no additional noise and minimal distortion. As a result, an
RF transformer is recommended in high frequency applica-
tions, especially undersampling, in which the performance of
a dual op amp differential driver may not be adequate. An RF
transformer has the added benefit of providing electrical isola-
tion between the signal source and the ADC. Однако, поскольку
lower cutoff frequency of most RF transformers is nominally a
few 100 kHz, a dual op amp differential driver may be more suit-
able in ac-coupling applications, where the spectral content of the
input signal falls below the cutoff frequency of a suitable RF
трансформатора.
Figure 32 is a suggested transformer circuit using a Mini-
Circuits RF transformer, model #T4-6T, which has an imped-
ance ratio of four (turns ratio of 2). The 1:4 impedance ratio
requires the 200 Ω secondary termination for optimum power
transfer and VSWR. The centertap of the transformer provides
a convenient means of level-shifting the input signal to a de-
sired common-mode voltage. Optimum performance can be
realized when the centertap is tied to CML of the AD9240
which is the common-mode bias level of the internal SHA.
VINA
CML
VINB
AD9240
0,1 F
200
MINI-CIRCUITS
T4-6T
50
Рисунок 32. Transformer Coupled Input
Transformers with other turns ratios may also be selected to
optimize the performance of a given application. For example, a
given input signal source or amplifier may realize an improve-
ment in distortion performance at reduced output power levels
and signal swings. Hence, selecting a transformer with a higher
impedance ratio (ie, Mini-Circuits T16-6T with a 1:16 imped-
ance ratio) effectively “steps up” the signal level, further reduc-
ing the driving requirements of the signal source.
AD9240
REV.
–14–
AC Coupling with Op Amps
As previously stated, a dual op amp differential driver may be
more suitable in applications in which the spectral content of the
input signal falls below the cutoff frequency of a suitable RF
transformer and/or the cost of an RF transformer and a low
distortion driver for the transformer is prohibitive.
The ac-coupled differential driver shown in Figure 33 is best
suited for ± 5 V systems in which the input signal is ground
referenced. In this case, V
CM
will be 0 V. This driver circuit can
achieve performance similar to an RF transformer over the
AD9240's full Nyquist bandwidth of 5 MHz. However, unlike
the RF transformer, the lower cutoff frequency can be arbitrarily
set low by adjusting the RC time constant formed by C
C
и
R
B
/2. C
N
, in combination with R
S
, can be used to limit the con-
tribution of op amp-generated noise at higher frequencies. Низкий
cost, high performance dual op amps operating from ± 5 V such
as the AD8056 and AD8058, are excellent choices for this appli-
cation and are capable of maintaining 78 dB SNR and 83 dB
THD at 1 MHz (5 V span). An optional resistor R
O
может быть
added to U1B to achieve a similar group delay as U1A, potentially
improving overall distortion performance. A resistor divider net-
work formed by R
B
centers the inputs of the AD9240 around
AVDD/2 to achieve its optimum distortion performance.
V
CM
ИСТОЧНИК
R
O
C
N
R
B
5K
R
S
C
C
0,1 F
V
КС
R
B
5K
C
C
0,1 F
V
КС
U1A
U1B
R
S
R
B
5K
R
B
5K
Рисунок 33. AC Coupling of Op Amps
DC Coupling with Op Amps
The dc-coupled differential driver in Figure 34 is best suited for
± 5 V systems in which the input signal is ground referenced and
optimum distortion performance is desired. This driver circuit
provides the ability to level-shift the input signal to within the
common-mode range of the AD9240. The two op amps are
configured as matched differential amps with the input signal
applied to opposing inputs to provide the differential output.
The common-mode offset voltage is applied to the noninverting
resistor network, which provides the proper level shifting.
AD9631 is given as the amplifier of choice in this application
due to its superior distortion performance for relatively large
output swings and wide bandwidth. If cost or space are factors,
the AD8056 dual op amp will save on both, but at the cost of
slightly increased distortion with large signal levels. Figure 34
also illustrates the use of protection diodes, which are used to
protect the AD9240 from any fault condition in which the op
amps outputs inadvertently go above V
DD
or below GND.
VINA
VINB
CML
AD9240
390
390
V
В
V
CML
–VIN
V
CML
+VIN
AVDD
390
390
220
390
AVDD
390
220
390
AD9631
AD9631
2.5k
33
100
0,1 F
1 F
0,1 F
OP113
33
390
0,1 F
0,1 F
Рисунок 34. Differential Driver with Level-Shifting
Single Supply DC-Coupled Driver
The circuit of Figure 33 can be easily modified for a single
supply, dc-coupled application. This is done by biasing V
CM
к
AVDD/2, the normal common-mode level in a single supply
системы. Since the outputs of the op amps are centered at
AVDD/2, the ac coupling network of C
C
and R
B
can be removed.
With this done, the differential driving pair can now be run from
a single supply.
SINGLE-ENDED MODE OF OPERATION
The AD9240 can be configured for single-ended operation
using dc or ac coupling. In either case, the input of the A/D
must be driven from an operational amplifier that will not de-
grade the A/D's performance. Because the A/D operates from a
single supply, it will be necessary to level-shift ground-based
bipolar signals to comply with its input requirements. Both dc
and ac coupling provide this necessary function, but each
method results in different interface issues which may influence
the system design and performance.
DC COUPLING AND INTERFACE ISSUES
Many applications require the analog input signal to be dc
coupled to the AD9240. An operational amplifier can be con-
figured to rescale and level-shift the input signal so it is compat-
ible with the selected input range of the A/D. The input range
to the A/D should be selected on the basis of system perfor-
mance objectives as well as the analog power supply availability
since this will place certain constraints on the op amp selection.
Many of the new high performance op amps are specified for
only ± 5 V operation and have limited input/output swing capa-
ностей. Hence, the selected input range of the AD9240 should
be sensitive to the headroom requirements of the particular op
amp to prevent clipping of the signal. Also, since the output of a
dual supply amplifier can swing below –0.3 V, clamping its
output should be considered in some applications.
In some applications, it may be advantageous to use an op amp
specified for single supply +5 V operation since it will inherently
limit its output swing to within the power supply rails. Rail-to-
rail output amplifiers such as the AD8041 allow the AD9240 to
be configured with larger input spans which improves the noise
производительность.
AD9240
REV.
–15–
If the application requires the largest single-ended input range
(ie, 0 V to 5 V) of the AD9240, the op amp will require larger
supplies to drive it. Various high speed amplifiers in the Op
Amp Selection Guide of this data sheet can be selected to
accommodate a wide range of supply options. Once again,
clamping the output of the amplifier should be considered for
these applications. Alternatively, a single-ended to differential
op amp driver circuit using the AD8042 could be used to
achieve the 5 V input span while operating from a single +5 V
supply as discussed in the previous section.
Two dc coupled op amp circuits using a noninverting and
inverting topology are discussed below. Although not shown,
the noninverting and inverting topologies can be easily config-
ured as part of an antialiasing filter by using a Sallen-Key or
Multiple-Feedback topology, respectively. An additional RC
network can be inserted between the op amp's output and the
AD9240 input to provide a real pole.
Simple Op Amp Buffer
In the simplest case, the input signal to the AD9240 will already
be biased at levels in accordance with the selected input range.
It is simply necessary to provide an adequately low source im-
pedance for the VINA and VINB analog input pins of the A/D.
Figure 35 shows the recommended configuration for a single-
ended drive using an op amp. In this case, the op amp is shown
in a noninverting unity gain configuration driving the VINA pin.
The internal reference drives the VINB pin. Note that the addi-
tion of a small series resistor of 30 Ω to 50 Ω connected to VINA
and VINB will be beneficial in nearly all cases. Обратитесь к
Analog Input Operation section for a discussion on resistor
выбора. Figure 35 shows the proper connection for a 0 V to
5 V input range. Alternative single ended input ranges of 0 V to
2 × VREF can also be realized with the proper configuration of
VREF (refer to the section, Using the Internal Reference).
10 F
VINA
VINB
SENSE
AD9240
0,1 F
R
S
+ V
–V
R
S
VREF
5V
0В
U1
2.5V
Рисунок 35. Single-Ended AD9240 Op Amp Drive Circuit
Op Amp with DC Level-Shifting
Figure 36 shows a dc-coupled level-shifting circuit employing an
op amp, A1, to sum the input signal with the desired dc offset.
Configuring the op amp in the inverting mode with the given
resistor values results in an ac signal gain of –1. If the signal
inversion is undesirable, interchange the VINA and VINB con-
nections to reestablish the original signal polarity. The dc volt-
age at VREF sets the common-mode voltage of the AD9240. Для
example, when VREF = 2.5 V, the output level from the op amp
will also be centered around 2.5 V. The use of ratio matched,
thin-film resistor networks will minimize gain and offset errors.
An optional pull-up resistor, R
P
, may also be used to reduce the
output load on VREF to ± 1 mA.
0В
Постоянный ток
+VREF
–VREF
VINA
VINB
AD9240
0,1 F
500 *
0,1 F
500 *
A1
Северная Каролина
Северная Каролина
+ V
КС
500 *
R
S
VREF
500 *
R
S
R
P
**
AVDD
*OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D
**OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE
Рисунок 36. Single-Ended Input With DC-Coupled Level-Shift
AC COUPLING AND INTERFACE ISSUES
For applications where ac coupling is appropriate, the op amp’s
output can be easily level-shifted to the common-mode voltage,
V
CM
, of the AD9240 via a coupling capacitor. Это
advantage of allowing the op amps common-mode level to be
symmetrically biased to its midsupply level (ie, (V
КС
+ V
EE
)/
2). Op amps that operate symmetrically with respect to their
power supplies typically provide the best ac performance as well
as greatest input/output span. Hence, various high speed/
performance amplifiers that are restricted to +5 V/–5 V op-
eration and/or specified for +5 V single-supply operation can be
easily configured for the 5 V or 2 V input span of the AD9240,
соответственно. The best ac distortion performance is achieved
when the A/D is configured for a 2 V input span and common-
mode voltage of 2.5 V. Note that differential transformer
coupling, which is another form of ac coupling, should be
considered for optimum ac performance.
Simple AC Interface
Figure 37 shows a typical example of an ac-coupled, single-
ended configuration. The bias voltage shifts the bipolar,
ground-referenced input signal to approximately VREF.
value for C1 and C2 will depend on the size of the resistor, R.
The capacitors, C1 and C2, are typically a 0.1 µ F ceramic and
10 µ F tantalum capacitor in parallel to achieve a low cutoff
frequency while maintaining a low impedance over a wide fre-
quency range. The combination of the capacitor and the resistor
form a high-pass filter with a high-pass –3 dB frequency deter-
mined by the equation,
е
–3 dB
= 1/(2 × π × R × ( C 1 + C 2))
C2
VINA
VINB
SENSE
AD9240
C1
R
+5V
–5V
R
S
VREF
+VREF
0В
–VREF
V
В
C2
C1
R
S
Figure 37. AC-Coupled Input
The low impedance VREF voltage source biases both the VINB
input and provides the bias voltage for the VINA input. Фигура
37 shows the VREF configured for 2.5 V. Thus the input range
of the A/D is 0 V to 5 V. Other input ranges could be selected
by changing VREF but the A/D's distortion performance will
AD9240
REV.
–16–
degrade slightly as the input common-mode voltage deviates
from its optimum level of 2.5 V.
Alternative AC Interface
Figure 38 shows a flexible ac-coupled circuit which can be con-
figured for different input spans. Since the common-mode
voltage of VINA and VINB are biased to midsupply indepen-
dent of VREF, VREF can be pin-strapped or reconfigured to
achieve input spans between 2 V and 5 V pp. The AD9240’s
CMRR along with the symmetrical coupling RC networks will
reject both power supply variations and noise. The resistors, R,
establish the common-mode voltage. They may have a high value
(eg, 5 k Ω ) to minimize power consumption and establish a low
cutoff frequency. The capacitors, C1 and C2, are typically a
0.1 µ F ceramic and 10 µ F tantalum capacitor in parallel to
achieve a low cutoff frequency while maintaining a low imped-
ance over a wide frequency range. R
S
isolates the buffer ampli-
fier from the A/D input. The optimum performance is achieved
when VINA and VINB are driven via symmetrical networks.
The high pass f
–3 dB
point can be approximated by the equation,
е
–3 dB
= 1/(2 × π × R /2 × ( C 1 + C 2))
C2
VINA
VINB
AD9240
C1
R
+5V
–5V
R
S
V
В
C1
C2
R
R
S
+5V
R
R
+5V
Figure 38. AC-Coupled Input-Flexible Input Span,
V
CM
= 2.5 V
OP AMP SELECTION GUIDE
Op amp selection for the AD9240 is highly dependent on a
particular application. In general, the performance requirements
of any given application can be characterized by either time
domain or frequency domain parameters. In either case, one
should carefully select an op amp that preserves the perfor-
mance of the A/D. This task becomes challenging when one
considers the AD9240's high performance capabilities coupled
with other external system level requirements such as power
consumption and cost.
The ability to select the optimal op amp may be further compli-
cated by limited power supply availability and/or limited accept-
able supplies for a desired op amp. Newer, high performance op
amps typically have input and output range limitations in accor-
dance with their lower supply voltages. As a result, some op
amps will be more appropriate in systems where ac-coupling is
allowable. When dc-coupling is required, op amps without
headroom constraints such as rail-to-rail op amps or ones where
larger supplies can be used should be considered. Следующие
section describes some op amps currently available from Analog
Devices. The system designer is always encouraged to contact
the factory or local sales office to be updated on Analog De-
vices' latest amplifier product offerings. Highlights of the areas
where the op amps excel and where they may limit the perfor-
mance of the AD9240 are also included.
AD9631: 220 MHz Unity GBW, 16 ns Settling to 0.01%,
± 5 V Supplies
Best Applications: Best AC Specs, Low Noise,
AC-Coupled
Limits: Usable Input/Output Range, Power
Потребление
AD8047: 130 MHz Unity GBW, 30 ns Settling to 0.01%,
± 5 V Supplies
Best Applications: Good AC Specs, Low Noise,
AC-Coupled
Limits: THD > 5 MHz, Usable Input Range
AD8042: Dual AD8041
Best Applications: Differential and/or Low Imped-
ance Input Drivers
Limits: Noise with 2 V Input Range
REFERENCE CONFIGURATIONS
For the purpose of simplicity, the figures associated with this
section on internal and external reference operation do not
show recommended matching series resistors for VINA and
VINB. Please refer to section Driving the Analog Inputs, Intro-
duction, for a discussion of this topic. The figures do not show
the decoupling network associated with the CAPT and CAPB
булавки. Please refer to the Reference Operation section for a discus-
sion of the internal reference circuitry and the recommended
decoupling network shown in Figure 30.
USING THE INTERNAL REFERENCE
Single-Ended Input with 0 to 2 VREF Range
Figure 39 shows how to connect the AD9240 for a 0 V to 2 V or
0 V to 5 V input range via pin strapping the SENSE pin. An
intermediate input range of 0 to 2 × VREF can be established
using the resistor programmable configuration in Figure 41 and
connecting VREF to VINB.
10 F
VINA
VREF
AD9240
0,1 F
VINB
2xVREF
0В
SHORT FOR 0 TO 2V
INPUT SPAN
SENSE
SHORT FOR 0 TO 5V
INPUT SPAN
REFCOM
Рисунок 39. Internal Reference (2 V pp Input Span,
V
CM
= 1 V, or 5 V pp Input Span, V
CM
= 2.5 V)
In either case, both the common-mode voltage and input span
are directly dependent on the value of VREF. More specifically,
the common-mode voltage is equal to VREF while the input
span is equal to 2 × VREF. Thus, the valid input range extends
from 0 to 2 × VREF. When VINA is ≤ 0 V, the digital output
will be 0000 Hex; when VINA is ≥ 2 × VREF, the digital output
will be 3FFF Hex.
Shorting the VREF pin directly to the SENSE pin places the
internal reference amplifier in unity-gain mode and the result-
ant VREF output is 1 V. The valid input range is, therefore, 0 V
to 2 V. Shorting the SENSE pin directly to the REFCOM pin
configures the internal reference amplifier for a gain of 2.5 and
AD9240
REV.
–17–
the resultant VREF output is 2.5 V. The valid input range thus
becomes 0 V to 5 V. The VREF pin should be bypassed to the
REFCOM pin with a 10 µ F tantalum capacitor in parallel with a
low-inductance 0.1 µ F ceramic capacitor.
Single-Ended or Differential Input, V
CM
= 2.5 V
Figure 37 shows the single-ended configuration that gives the
best SINAD performance. To optimize dynamic specifications,
center the common-mode voltage of the analog input at
approximately by 2.5 V by connecting VINB to VREF, a low-
impedance 2.5 V source. As described above, shorting the
SENSE pin directly to the REFCOM pin results in a 2.5 V
reference voltage and a 5 V pp input span. The valid range
for input signals is 0 V to 5 V. The VREF pin should be by-
passed to the REFCOM pin with a 10 µ F tantalum capacitor in
parallel with a low inductance 0.1 µ F ceramic capacitor.
This reference configuration could also be used for a differential
input in which VINA and VINB are driven via a transformer as
shown in Figure 32. In this case, the common-mode voltage,
V
CM
, is set at midsupply by connecting the transformer's center
tap to CML of the AD9240. VREF can be configured for 1 V
or 2.5 V by connecting SENSE to either VREF or REFCOM
соответственно. Note that the valid input range for each of the
differential inputs is one half of the single-ended input and thus
becomes V
CM
– VREF/2 to V
CM
+ VREF/2.
0,1 F
10 F
VINA
VINB
VREF
SENSE
REFCOM
AD9240
5V
0В
2.5V
Рисунок 40. Internal Reference—5 V pp Input Span,
V
CM
= 2.5 V
Resistor Programmable Reference
Figure 41 shows an example of how to generate a reference
voltage other than 1 V or 2.5 V with the addition of two external
resistors and a bypass capacitor. Use the equation,
VREF = 1 V × (1 + R 1/ R 2),
to determine appropriate values for R1 and R2. These resistors
should be in the 2 k Ω to 100 k Ω range. For the example
shown, R1 equals 2.5 k Ω and R2 equals 5 k Ω . From the equa-
tion above, the resultant reference voltage on the VREF pin is
1.5 V. This sets the input span to be 3 V pp. To assure stabil-
ity, place a 0.1 µ F ceramic capacitor in parallel with R1.
The common-mode voltage can be set to VREF by connecting
VINB to VREF to provide an input span of 0 to 2 × VREF.
Alternatively, the common-mode voltage can be set to 2.5 V
by connecting VINB to a low impedance 2.5 V source. Для
the example shown, the valid input signal range for VINA is 1 V
to 4 V since VINB is set to an external, low impedance 2.5 V
источника. The VREF pin should be bypassed to the REFCOM pin
with a 10 µ F tantalum capacitor in parallel with a low induc-
tance 0.1 µ F ceramic capacitor.
1.5V
C1
0,1 F
10 F
VINA
VINB
VREF
SENSE
REFCOM
AD9240
4V
1V
2.5V
R1
2.5k
R2
5K
0,1 F
Figure 41. Resistor Programmable Reference (3 V pp
Input Span, V
CM
= 2.5 V)
USING AN EXTERNAL REFERENCE
Using an external reference may enhance the dc performance of
the AD9240 by improving drift and accuracy. Figures 42
through 44 show examples of how to use an external reference
with the A/D. Table III is a list of suitable voltage references
from Analog Devices. To use an external reference, the user
must disable the internal reference amplifier and drive the
VREF pin. Connecting the SENSE pin to AVDD disables the
internal reference amplifier.
Таблица III. Suitable Voltage References
Первоначальный
Operating
Выходной
Дрейф
Точность
Ток
Напряжение
(ppm/ C)
% (max)
( A)
Внутренний
1,00
26
1,4
Не Доступно
REF191 2.048
5–25
0.1–0.5
45
Внутренний
2,50
26
1,4
Не Доступно
REF192 2.50
5–25
0.08–0.4
45
AD780
2,50
3–7
0.04–0.2
1000
The AD9240 contains an internal reference buffer, A2 (see
Figure 29), that simplifies the drive requirements of an external
ссылки. The external reference must be able to drive a ≈ 5 k Ω
( ± 20%) load. Note that the bandwidth of the reference buffer is
deliberately left small to minimize the reference noise contribu-
Тион. As a result, it is not possible to change the reference volt-
age rapidly in this mode without the removal of the CAPT/
CAPB Decoupling Network, and driving these pins directly.
AD9240
REV.
–18–
Variable Input Span with V
CM
= 2.5 V
Figure 42 shows an example of the AD9240 configured for an
input span of 2 × VREF centered at 2.5 V. An external 2.5 V
reference drives the VINB pin thus setting the common-mode
voltage at 2.5 V. The input span can be independently set by a
voltage divider consisting of R1 and R2, which generates the
VREF signal. A1 buffers this resistor network and drives VREF.
Choose this op amp based on accuracy requirements. Это
essential that a minimum of a 10 µ F capacitor in parallel with a
0.1 µ F low inductance ceramic capacitor decouple the reference
output to ground.
2.5V+VREF
2.5V–VREF
2.5V
+5 V
0,1 F
22 F
VINA
VINB
VREF
SENSE
AD9240
+5 V
R2
0,1 F
A1
R1
0,1 F
2.5V
REF
Figure 42. External Reference, V
CM
= 2.5 V (2.5 V on VINB,
Resistor Divider to Make VREF)
Single-Ended Input with 0 to 2 VREF Range
Figure 43 shows an example of an external reference driving
both VINB and VREF. In this case, both the common mode
voltage and input span are directly dependent on the value of
VREF. More specifically, the common-mode voltage is equal to
VREF while the input span is equal to 2 × VREF. Таким образом,
valid input range extends from 0 to 2 × VREF. If, for example,
the REF191, a 2.048 external reference, were selected, the valid
input range extends from 0 V to 4.096 V. In this case, 1 LSB of
the AD9240 corresponds to 0.250 mV. It is essential that a
minimum of a 10 µ F capacitor in parallel with a 0.1 µ F low induc-
tance ceramic capacitor decouple the reference output to ground.
2xREF
0В
+5 V
10 F
VINA
VINB
VREF
SENSE
AD9240
+5 V
0,1 F
VREF
0,1 F
0,1 F
Рисунок 43. Input Range = 0 V to 2 × VREF
Low Cost/Power Reference
The external reference circuit shown in Figure 44 uses a low cost
1.225 V external reference (eg, AD580 or AD1580) along with an
op amp and transistor. The 2N2222 transistor acts in conjunction
with 1/2 of an OP282 to provide a very low impedance drive for
VINB. The selected op amp need not be a high speed op amp and
may be selected based on cost, power and accuracy.
3.75V
1.25V
+5 V
10 F
VINA
VINB
VREF
SENSE
AD9240
+5 V
0,1 F
316
1k
0,1 F
1 / 2
OP282
10 F
0,1 F
7.5k
AD1580
1k
1k
820
+5 V
2N2222
1.225V
Диаграмма 44. External Reference Using the AD1580 and Low
Impedance Buffer
DIGITAL INPUTS AND OUTPUTS
Digital Outputs
The AD9240 output data is presented in positive true straight
binary for all input ranges. Table IV indicates the output data
formats for various input ranges regardless of the selected input
диапазона. A twos complement output data format can be created by
inverting the MSB.
Таблица IV. Output Data Format
Входного сигнала (V)
Condition (V)
Digital Output
OTR
VINA – VINB < –VREF
00 0000 0000 0000 1
VINA – VINB = –VREF
00 0000 0000 0000 0
VINA – VINB = 0
10 0000 0000 0000 0
VINA – VINB = +VREF – 1 LSB 11 1111 1111 1111 0
VINA – VINB ≥ +VREF
11 1111 1111 1111 1
Out Of Range (OTR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the converter. OTR is a digital
output that is updated along with the data output corresponding
to the particular sampled analog input voltage. Hence, OTR
has the same pipeline delay (latency) as the digital data. Это
LOW when the analog input voltage is within the analog input
диапазона. It is HIGH when the analog input voltage exceeds the
input range as shown in Figure 45. OTR will remain HIGH
until the analog input returns within the input range and an-
other conversion is completed. By logical ANDing OTR with
the MSB and its complement, overrange high or underrange low
conditions can be detected. Table V is a truth table for the over/
underrange circuit in Figure 46 which uses NAND gates. Sys-
tems requiring programmable gain conditioning of the AD9240
input signal can immediately detect an out-of-range condition,
thus eliminating gain selection iterations. Also, OTR can be
used for digital offset and gain calibration.
111111 1111 1111
111111 1111 1111
111111 1111 1110
OTR
–FS
+FS
–FS+1/2 LSB
+FS –1/2 LSB
–FS –1/2 LSB
+FS –1 1/2 LSB
000000 0000 0001
000000 0000 0000
000000 0000 0000
1
0
0
0
0
1
OTR
DATA OUTPUTS
Рисунок 45. Output Data Format
AD9240
REV.
–19–
Table V. Out-of-Range Truth Table
OTR
MSB
Analog Input Is
0
0
In Range
0
1
In Range
1
0
Underrange
1
1
Overrange
OVER = “1”
UNDER = “1”
MSB
OTR
MSB
Рисунок 46. Overrange or Underrange Logic
Digital Output Driver Considerations (DRVDD)
The AD9240 output drivers can be configured to interface with
+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V
соответственно. The AD9240 output drivers are sized to provide
sufficient output current to drive a wide variety of logic families;
large drive currents tend to cause glitches on the supplies and may
affect SINAD performance. Applications requiring the AD9240 to
drive large capacitive loads or large fanout may require additional
decoupling capacitors on DRVDD. In extreme cases, external
buffers or latches may be required.
Clock Input and Considerations
The AD9240 internal timing uses the two edges of the clock
input to generate a variety of internal timing signals. The clock
input must meet or exceed the minimum specified pulsewidth
high and low (t
CH
и т
CL
) specifications for the given A/D, as
defined in the Switching Specifications at the beginning of the
data sheet, to meet the rated performance specifications. Для
example, the clock input to the AD9240 operating at 10 MSPS
may have a duty cycle between 45% to 55% to meet this timing
requirement since the minimum specified t
CH
и т
CL
is 45 ns.
For clock rates below 10 MSPS, the duty cycle may deviate
from this range to the extent that both t
CH
и т
CL
будут удовлетворены.
All high speed high resolution A/Ds are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
В
), due only to aperture jitter (t
), can be
calculated with the following equation:
SNR = 20 log
10
[1/(2 π f
В
т
)]
In the equation, the rms aperture jitter, t
, represents the root-
sum square of all the jitter sources, which include the clock
input, analog input signal and A/D aperture jitter specification.
For example, if a 5.0 MHz full-scale sine wave is sampled by an
A/D with a total rms jitter of 15 ps, the SNR performance of the
A/D will be limited to 66.5 dB. Undersampling applications are
particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9240. As such, supplies for clock drivers should be separated
from the A/D output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter crystal controlled oscil-
lators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing or other method), it
should be retimed by the original clock at the last step.
Most of the power dissipated by the AD9240 is from the analog
power supply; however, lower clock speeds will reduce digital
current slightly. Figure 47 shows the relationship between power
and clock rate.
CLOCK FREQUENCY – MHz
400
200
2
20
4
6
8
10
12
14
16
18
380
300
260
240
220
360
340
280
320
POWER – mW
Рисунок 47. Power Consumption vs. Clock Frequency
(R
BIAS
= 2 k Ω )
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
системы. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes.
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation and ground plane.
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
производительность.
It is important to design a layout that prevents noise from coupling
onto the input signal. Digital signals should not be run in paral-
lel with input signal traces and should be routed away from the
input circuitry. While the AD9240 features separate analog and
digital ground pins, it should be treated as an analog component.
The AVSS, DVSS and DRVSS pins must be joined together
directly under the AD9240. A solid ground plane under the A/D
is acceptable if the power and ground return currents are care-
fully managed. Alternatively, the ground plane under the A/D
may contain serrations to steer currents in predictable directions
where cross-coupling between analog and digital would other-
wise be unavoidable. The AD9240/EB ground layout, shown in
Figure 57, depicts the serrated type of arrangement. The analog
and digital grounds are connected by a jumper below the A/D.
AD9240
REV.
–20–
Analog and Digital Supply Decoupling
The AD9240 features separate analog and digital supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals.
FREQUENCY – kHz
120
PSRR – dBFS
100
1000
80
60
40
100
10
1
AVDD
DVDD
Figure 48. PSRR от частоты
Figure 48 shows the power supply rejection ratio vs. frequency
for a 200 mV pp ripple applied to both AVDD and DVDD.
In general, AVDD, the analog supply, should be decoupled to
AVSS, the analog common, as close to the chip as physically
это возможно. Figure 49 shows the recommended decoupling for the
analog supplies; 0.1 µ F ceramic chip capacitors should provide
adequately low impedance over a wide frequency range. Внимание
that the AVDD and AVSS pins are co-located on the AD9240
to simplify the layout of the decoupling capacitors and provide
the shortest possible PCB trace lengths. The AD9240/EB power
plane layout, shown in Figure 58, depicts a typical arrangement
using a multilayer PCB.
0,1 F
AVDD
УСБТ
AD9240
0,1 F
AVDD
УСБТ
Рис 49. Analog Supply Decoupling
The CML is an internal analog bias point used internally by the
AD9240. This pin must be decoupled with at least a 0.1 µ F
capacitor as
shown in Figure 50. The dc level of CML is ap-
proximately AVDD/2. This voltage should be buffered if it is to
be used for any external biasing.
0,1 F
CML
AD9240
Рисунок 50. CML Decoupling
The digital activity on the AD9240 chip falls into two general
categories: correction logic and output drivers. Внутренний
correction logic draws relatively small surges of current, mainly
during the clock transitions. The output drivers draw large
current impulses while the output bits are changing. The size
and duration of these currents are a function of the load on the
output bits: large capacitive loads are to be avoided. Note that the
internal correction logic of the AD9240 is referenced DVDD
while the output drivers are referenced to DRVDD.
The decoupling shown in Figure 51, a 0.1 µ F ceramic chip
capacitor, is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Применения
involving greater digital loads should consider increasing the
digital decoupling proportionally and/or using external buffers/
latches.
0,1 F
DVDD
DVSS
AD9240
DRVDD
DRVSS
0,1 F
Figure 51. Digital Supply Decoupling
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the PCB to reduce low-frequency
ripple to negligible levels. For more information regarding the
placement of decoupling capacitors, refer to the AD9240/EB
schematic and layouts in Figures 54–58.
ПРИМЕНЕНИЕ
Direct IF Down Conversion Using the AD9240
Sampling IF signals above an ADC's baseband region (ie, dc
to F
S
/2) is becoming increasingly popular in communication
приложений. This process is often referred to as Direct IF Down
Conversion or Undersampling. There are several potential benefits
in using the ADC to alias (or mix) down a narrowband or wide-
band IF signal. First and foremost is the elimination of a
complete mixer stage with its associated amplifiers and filters
reducing cost and power dissipation. Second is the ability to
apply various DSP techniques to perform such functions as
filtering, channel selection, quadrature demodulation, data
reduction, detection, etc. A detailed discussion on using this
technique in digital receivers can be found in Analog Devices
Application Notes AN-301 and AN-302.
In Direct IF Down Conversion applications, one exploits the
inherent sampling process of an ADC in which an IF signal
lying outside the baseband region can be aliased back into the
baseband region in a similar manner that a mixer will downconvert
an IF signal. Similar to the mixer topology, an image rejection
filter is required to limit other potential interfering signals from
also aliasing back into the ADC's baseband region. A tradeoff
exists between the complexity of this image rejection filter and
the sample rate as well as dynamic range of the ADC.
Until recently, the actual implementation of Direct IF Down
Conversion has been limited by the lack of cost-effective ADCs
with sufficiently wide dynamic range and high sample rates for
IFs beyond 10.7 MHz. Since the performance of the AD9240
in the differential mode of operation extends well beyond its
baseband region, it may be well suited as a mix-down converter
in narrowband as well as some wideband applications. Кроме того,
with the full-power bandwidth of the AD9240 extending beyond
60 MHz, various IF frequencies exist over this frequency range
in which the AD9240 maintains excellent dynamic performance.
Figure 52 shows the AD9240 configured in an IF sampling
application at 37.5 MHz. To reduce the complexity of the
digital demodulator in many quadrature demodulation applica-
tions, the IF frequency and/or sample rate are selected such that
AD9240
REV.
–21–
the bandlimited IF signal aliases back into the center of the ADC’s
baseband region (ie F
S
/4). At a sample rate of 10 MSPS, an
image of the IF signal centered at 37.5 MHz will be aliased back
to 2.5 MHz which corresponds to one quarter of the sample rate
(ie F
S
/4). Note, the IF signal in this case will have undergone a
frequency inversion that may easily be corrected for in the digital
домена.
200
0,1 F
AD9240
VINA
CML
VINB
50
AD8009
50
280
93,1
AD8009
200
22,1
50
SAW FILTER
ПРОИЗВОДСТВО
G
1
= 20dB
G
2
= 12dB
MINI-CIRCUITS
T4-6T
Диаграмма 52. Simplified AD9240 IF Sampling Circuit
To maximize its distortion performance, the AD9240 is config-
ured in the differential mode using a transformer. Preceding the
AD9240 is a bandpass filter and a 32 dB gain stage. A large
gain stage may be required to compensate for the high insertion
losses of a SAW filter used for image rejection. The gain stage
will also provide adequate isolation for the SAW filter from the
transient currents associated with AD9240's input stage.
The gain stage can be realized using one or two cascaded AD8009
op amps. The AD8009 is a low cost current-feedback op amp
having a third order intercept of 33 dB for a gain of +10 MHz
at 37.5 MHz. A passive bandpass filter is required after the
AD8009 to reduce the resulting second order distortion prod-
ucts and limit its out-of-band noise. The specifications of this
filter are application dependent and will affect both the total
distortion and noise performance of this circuit.
Figure 53 shows the single-tone SNR and SFDR performance of
the AD9240 configured in the 2 V and 5 V span without using
the AD8009 gain stage. Only a slight degradation in SNR perfor-
mance (ie, 1 dB) was noted with the inclusion of the AD8009
gain stage and a bandpass filter. Note, the tradeoff in SNR and
SFDR (dBFS) performance between the 5 V and 2 V spans at
different signal levels.
INPUT POWER LEVEL – dBFS
40
-30
-80
–70
–60
-40
80
60
50
70
30
20
WORST CASE SPURIOUS AND SNR – dBc
10
0
-50
-20
-10
0
SFDR w/5V SPAN
SFDR w/2V SPAN
SNR w/5V SPAN
SNR w/2V SPAN
Рис 53. Single-Tone SNR/SFDR vs. Input Amplitude
@ 37.45 MHz
Figure 54 compares the two tone SFDR performance of the
AD9240 in the 2 V span with and without the use of the AD8009
gain stage. No degradation in distortion performance was noted
with the inclusion of the AD8009 gain stage provided that the
AD8009 2nd order distortion products are sufficiently attenu-
ated by the bandpass filter.
INPUT POWER LEVEL (f
1
= F
2
) – dBFS
40
-90
-30
-80
–70
–60
-40
100
90
80
60
50
70
30
20
WORST CASE SPURIOUS – dBc AND dBFS
10
0
-50
-20
-10
0
w/o AD8009 – dBFS
w/AD8009 – dBFS
w/o AD8009 – dBc
w/AD8009 – dBc
85 dB REFERENCE LINE
Рисунок 54. Two Tone SFDR vs. Input Amplitude
@ F
1
= 36.40 MHz and f
2
= 38.60 MHz
AD9240
REV.
-22 -
2
3
AD817
V
EE
U3
R7
1k
C16
0,1
F
R8 316
Q1
2N2222
C17
10
F
16V
C18 0.1
F
R6 820
+5VA
TP25
R4
50
JP10
R3
15k
C12 0.1
F
R5 10k
C13
10
F
16V
V
В
V
OUT
GND
REF43
EXTERNAL REFERENCE DRIVE
U2
V
КС
C14
0,1
F
6
7
4
V
КС