AGND – 3/2 LSB

111 . . . 110 to 111 . . . 111

–FSR/2 + 5/2 LSB

100 . . . 010 to 100 . . . 011

–FSR/2 + 3/2 LSB

100 . . . 001 to 100 . . . 010

–FSR/2 + 1/2 LSB

100 . . . 000 to 100 . . . 001

NOTES

1

FSR is full-scale range and is 20 V for the ±10 V range and 10 V for the ±5 V

range, with V

REF

= 2.5 V.

2

1 LSB = FSR/16384 = 1.22 mV (±10 V—AD7865-1) and 610.4 mV (±5 V—

AD7865-1) with V

REF

= 2.5 V.

AD7865-2

Figure 3 shows the analog input section of the AD7865-2. Каждый

input can be configured for 0 V to 5 V operation or 0 V to 2.5 V

operation. For the 0 V to 5 V operation, the V

INxB

input is tied

to AGND and the input voltage is applied to V

INxA

input. For

0 V to 2.5 V operation, the V

INxA

and V

INxB

inputs are tied together

and the input voltage is applied to both. The V

INxA

and V

INxB

inputs are symmetrical and fully interchangeable. Thus for ease

of PCB layout on the 0 V to 5 V range the input voltage may be

applied to the V

INxB

input while the V

INxA

input is tied to AGND.

For the AD7865-2, R1 = 4 kΩ and R2 = 4 kΩ. Once again,

the designed code transitions occur on successive integer LSB

ценностей. Output coding is straight (natural) binary with 1 LSB

= FSR/16384 = 2.5 V/16384 = 0.153 mV, and 5 V/16384 =

0.305 mV, for 0 V to 2.5 V and 0 V to 5 V options respectively.

Table II shows the ideal input and output transfer function

for the AD7865-2.

AD7865-2

V

INxA

TRACK/

HOLD

TO ADC

REFERENCE

CIRCUITRY

TO INTERNAL

Компаратор

R1

6k

2.5V

REFERENCE

R2

V

INxB

V

REF

Рисунок 3. AD7865-2 Analog Input Structure

Table II. Ideal Input/Output Code Table for the AD7865-2

Аналоговый вход

1

Digital Output Code Transition

+FSR/2 – 3/2 LSB

2

111 . . . 110 to 111 . . . 111

+FSR/2 – 5/2 LSB

111 . . . 101 to 111 . . . 110

+FSR/2 – 7/2 LSB

111 . . . 100 to 111 . . . 101

AGND + 5/2 LSB

000 . . . 010 to 000 . . . 011

AGND + 3/2 LSB

000 . . . 001 to 000 . . . 010

AGND – 1/2 LSB

000 . . . 000 to 000 . . . 001

NOTES

1

FSR is full-scale range and is 0 V to 2.5 V and 0 V to 5 V for AD7865-2 with

V

REF

= 2.5 V.

2

1 LSB = FSR/16384 and is 0.153 mV (0 V to 2.5 V) and 0.305 mV (0 V to 5 V)

for AD7865-2) with V

REF

= 2.5 V.

REV. B

AD7865

–11–

AD7865-3

Figure 4 shows the analog input section of the AD7865-3.

analog input range is ±2.5 V on the V

INxA

input. The V

INxB

input can be left unconnected but if it is connected to a poten-

tial then that potential must be AGND.

AD7865-3

V

INxA

TRACK/

HOLD

TO ADC

REFERENCE

CIRCUITRY

TO INTERNAL

Компаратор

R1

R2

6k

2.5V

REFERENCE

V

INxB

V

REF

Рисунок 4. AD7865-3 Analog Input Structure

For the AD7865-3, R1 = 4 kΩ and R2 = 4 kΩ. В результате,

V

INxA

input should be driven from a low impedance source.

resistor input stage is followed by the high input impedance

stage of the track/hold amplifier.

The designed code transitions take place midway between suc-

cessive integer LSB values (ie, 1/2 LSB, 3/2 LSBs, 5/2 LSBs

etc.) LSB size is given by the formula, 1 LSB = FSR/16384.

Output coding is twos complement binary with 1 LSB = FSR/

16384 = 5 V/16384 = 610.4 µV. The ideal input/output transfer

function for the AD7865-3 is shown in Table III.

Table III. Ideal Input/Output Code Table for the AD7865-3

Аналоговый вход

1

Digital Output Code Transition

+FSR/2 – 3/2 LSB

2

011 . . . 110 to 011 . . . 111

+FSR/2 – 5/2 LSB

011 . . . 101 to 011 . . . 110

+FSR/2 – 7/2 LSB

011 . . . 100 to 011 . . . 101

AGND + 3/2 LSB

000 . . . 001 to 000 . . . 010

AGND + 1/2 LSB

000 . . . 000 to 000 . . . 001

AGND – 1/2 LSB

111 . . . 111 to 000 . . . 000

AGND – 3/2 LSB

111 . . . 110 to 111 . . . 111

–FSR/2 + 5/2 LSB

100 . . . 010 to 100 . . . 011

–FSR/2 + 3/2 LSB

100 . . . 001 to 100 . . . 010

–FSR/2 + 1/2 LSB

100 . . . 000 to 100 . . . 001

NOTES

1

FSR is full-scale range is 5 V, with V

REF

= 2.5 V.

2

1 LSB = FSR/16384 = 610.4 µV (±2.5 V—AD7865-3) with V

REF

= 2.5 V.

SELECTING A CONVERSION SEQUENCE

Any subset of the four channels V

IN1

to V

IN4

can be selected for

преобразования. The selected channels are converted in an ascending

порядка. For example if the channel selection includes V

IN4

, V

IN1

and V

IN3

then the conversion sequence will be V

IN1

, V

IN3

и

then V

IN4

. The conversion sequence selection may be made by

using either the hardware channel select input pins SL1 through

SL4 (if H /S is tied low) or programming the channel select

register (if H /S is tied high). A logic high on a hardware channel

select pin (or logic one in the channel select register) when

CONVST goes logic high, marks the associated analog input

channel for inclusion in the conversion sequence.

Figure 5 shows the arrangement used. The H /S SEL controls a

multiplexer that selects the source of the conversion sequence

information, ie, from the hardware channel select pins (SL1 to

SL4) or from the channel selection register. When a conversion

is started the output from the multiplexer is latched until the

end-of-the conversion sequence. The data bus bits DB0 to DB3

(DB0 representing Channel 1 through DB3 representing Chan-

nel 4) are bidirectional and become inputs to the channel select

register when RD is logic high and CS and WR are logic low.

The logic state on DB0 to DB3 is latched into the channel select

register when WR goes logic high. Figure 6 shows the loading

sequence for channel selection using software control. Когда

using software control to select the conversion sequence a write

is only required each time the conversion sequence needs

changing. This is because the channel select register will hold its

information until different information is written to it.

It should be noted that the hardware select Pins SL1 and SL2

are dual function. When H /S SEL is logic high (selecting the

conversion sequence using software control) they take the func-

tions CLK IN and INT /EXT CLK respectively. Therefore, the

logic inputs on these pins must be set according to the type of

operation required (see Using an External Clock). Also when

H /S SEL is high, the SL3 and SL4 logic inputs have no function

and can be tied either high or low, but should not be left fl oating.

DATA BUS

D0

D1

D2

D3

WR

CS

WR

CHANNEL

SELECT

REGISTER

SL1

SL2

SL3

SL4

HARDWARE CHANNEL

SELECT PINS

H/S

TRANSPARENT WHILE WAITING FOR CONVST.

LATCHED ON THE RISING EDGE OF CONVST AND

DURING A CONVERSION SEQUENCE.

MULTIPLEXER

LATCH

SEQUENCER

SELECT INDIVIDUAL

TRACK-AND-HOLDS

FOR CONVERSION

Рисунок 5. Channel Select Inputs and Registers

RD

WR

CS

DATA

т

16

т

17

т

14

т

15

DATA IN

т

13

Рисунок 6. Channel Selection via Software Control

REV. B

AD7865

-12 -

TIMING AND CONTROL

Reading Between Each Conversion in the Conversion Sequence

Figure 7 shows the timing and control sequence required to

obtain the optimum throughput rate from the AD7865. К

obtain the optimum throughput from the AD7865 the user must

read the result of each conversion as it becomes available.

timing diagram in Figure 7 shows a read operation each time the

EOC signal goes logic low. The timing in Figure 7 shows a

conversion on all four analog channels (SL1 to SL4 = 1, see

Selecting a Conversion Sequence), hence there are four EOC

pulses and four read operations to access the result of each of

the four conversions.

A conversion is initiated on the rising edge of CONVST . Это

places all four track/holds into hold simultaneously. New data

from this conversion sequence is available for the first channel

selected (A

IN1

) 2.4 µs later. The conversion on each subsequent

channel is completed at 2.4 µs intervals. The end of each con-

version is indicated by the falling edge of the EOC signal.

BUSY output signal indicates the end of conversion for all

selected channels (four in this case).

Data is read from the part via a 14-bit parallel data bus with

standard CS and RD signals. The CS and RD inputs are inter-

nally gated to enable the conversion result onto the data bus.

The data lines DB0 to DB13 leave their high impedance state

when both CS and RD are logic low. Therefore, CS may be

permanently tied logic low and the RD signal used to access the

conversion result. Since each conversion result is latched into its

output data register at the same time EOC goes logic low a

further option would be to tie the EOC and RD pins together

with CS tied logic low and use the rising edge of EOC to latch

the conversion result. Although the AD7865 has some special

features that permit reading during a conversion (eg, a sepa-

rate supply for the output data drivers, V

DRIVE

), for optimum

performance it is recommended that the read operation be

completed when EOC is logic low, ie, before the start of the

next conversion. Although Figure 7 shows the read operation

taking place during the EOC pulse, a read operation can take

place at any time. Figure 7 shows a timing specification called

“Quiet Time.” This is the amount of time that should be left

after a read operation and before the next conversion is initi-

ated. The quiet time heavily depends on data bus capacitance

but a figure of 50 ns to 150 ns is typical.

The signal labeled FRSTDATA (First Data Word) indicates to

the user that the pointer associated with the output data regis-

ters is pointing to the first conversion result by going logic high.

The pointer is reset to point to the first data location (ie, first

conversion result,) at the end of the first conversion just prior to

EOC going low. The pointer is incremented to point to the next

register (next conversion result) by a rising edge of RD only if

that conversion result is available. If a read takes place before

the next conversion is complete (as shown in Figure 7) then the

pointer is incremented at the end of that conversion when the

EOC pulse goes low. Hence, FRSTDATA in Figure 7 is seen to

go low just after to the second EOC pulse. Repeated read

operations during a conversion will continue to access the data

at the current pointer location until the pointer is incremented

at the end of that conversion. Note: FRSTDATA has an indeter-

minate logic state after initial power-up. This means that for the

first conversion sequence after power-up, the FRSTDATA

logic output may already be logic high before the end of the first

преобразования. This condition is indicated by the dashed line in

Рисунок 7. Also the FRSTDATA logic output may already be

high as a result of the previous read sequence as is the case after

the fourth read in Figure 7. The fourth read (rising edge of RD )

resets the pointer to the first data location. There, however,

FRSTDATA is already high when the next conversion sequence

начинается.

QUIET

ВРЕМЯ

т

CONV

т

BUSY

т

1

т

12

т

3

т

4

т

5

т

6

т

7

V

IN1

V

IN2

V

IN3

V

IN4

100ns

100ns

DATA

CONVST

BUSY

EOC

FRSTDATA

RD

CS

H/S SEL

SL1–SL4

т

2

т

ACQ

т

11

т

10

т

CONV

т

9

Рисунок 7. Timing Diagram for Reading During Conversion

REV. B

AD7865

–13–

Accessing the Output Data Registers

There are four Output Data Registers, one for each of the four

possible conversion results from a conversion sequence.

result of the first conversion in a conversion sequence is placed

in Register 1 and the second result is placed in Register 2 and so

on. For example if the conversion sequence V

IN1

, V

IN3

and V

IN4

is selected (see Selecting a Conversion Sequence) the results of

the conversion on V

IN1

, V

IN3

and V

IN4

are placed in Registers 1

to 3 respectively. The Output Data register pointer is reset to

point to Register 1 at the end of the first conversion in the

sequence, just prior to EOC going low. At this point the logic

output FRSTDATA will go logic high to indicate that the out-

put data register pointer is addressing Register 1. When CS and

RD are both logic low the contents of the addressed register are

enabled onto the data bus (DB0–DB13).

DB0 TO

DB13

O/P

ВОДИТЕЛЕЙ

OE #1

NOT VALID

(V

IN3

)

(V

IN1

)

(V

IN4

)

OE #2

OE #3

OE #4

2-BIT

COUNTER

V

DRIVE

О. Е.

RD

CS

RESET

ПРОИЗВОДСТВО

DATA REGISTERS

*THE POINTER WILL NOT BE INCREMENTED BY A RISING EDGE ON RD UNTIL

THE CONVERSION RESULT IS IN THE OUTPUT DATA REGISTER. THE POINTER

IS RESET WHEN THE LAST CONVERSION RESULT IS READ

FRSTDATA

POINTER*

AD7865

DECODE

Рисунок 8. Output Data Registers

When reading the output data registers after a conversion

sequence, ie, when BUSY goes low, the register pointer is

incremented on the rising edge of the RD signal as shown in

Рисунок 8. However, when reading the conversion results between

conversions in a conversion sequence the pointer will not be

incremented until a valid conversion result is in the register to

be addressed. In this case the pointer is incremented when the

conversion has ended and the result has been transferred to the

output data register. This happens when EOC goes low, there-

fore EOC may be used to enable the register contents onto the

data bus as described in Reading Between Conversions in the

Conversion Sequence. The pointer is reset to point to Register 1

on the rising edge of the RD signal when the last conversion

result in the sequence is being read. In the example shown in

Figure 8, this means that the pointer is set to Register 1 when

the contents of Register 3 are read.

Reading after the Conversion Sequence

Figure 9 shows the same conversion sequence as Figure 7. В

this case, however, the results of the four conversions (on V

IN1

to V

IN4

) are read after all conversions have finished, ie, when

BUSY goes logic low. The FRSTDATA signal goes logic high

at the end of the first conversion just prior to EOC going logic

low. As mentioned previously FRSTDATA has an indetermi-

nate state after initial power up, therefore FRSTDATA may

already be logic high. Unlike the case when reading during a

conversion the output data register pointer is incremented on

the rising edge of RD because the next conversion result is avail-

able in this case. This means FRSTDATA will go logic low after

the first rising edge on RD .

Successive read operations will access the remaining conversion

results in ascending channel order. Each read operation incre-

ments the output data register pointer. The read operation that

accesses the last conversion result causes the output data regis-

ter pointer to be reset so that the next read operation will access

the first conversion result again. This is shown in Figure 8 with

the fifth read after BUSY goes low accessi ng the result of the

conversion on V

IN1

. Thus the output data registers acts as a

circular buffer in which the conversion results may be continu-

ally accessed. The FRSTDATA signal will go high when the

first conversion result is available.

Data is enabled onto the data bus DB0 to DB13 using CS and

RD . Both CS and RD have the same functionality as described

in the previous section. There are no restrictions or performance

implications associated with the position of the read operations

after BUSY goes low, however there is a minimum time between

read operations that must be adhered to. Notice also that a “Quiet

Time” is needed before the start of the next conversion sequence.

т

10

т

8

т

4

т

3

т

6

т

1

QUIET

ВРЕМЯ

DATA

CONVST

BUSY

EOC

FRSTDATA

RD

CS

V

IN2

V

IN3

V

IN1

т

BUSY

т

2

т

10

т

7

V

IN1

V

IN4

Figure 9. Timing Diagram, Reading after the Conversion Sequences

REV. B

AD7865

-14 -

Using an External Clock

With the H /S SEL and INT/ EXT CLK pins tied to Logic 1, the

AD7865 will expect to be driven from an external clock.

highest external clock frequency allowed is 5 MHz. Это означает,

a conversion time of 3.2 µs compared to 2.4 µs using the inter-

nal clock. In some instances, however, it may be useful to use an

external clock when high throughput rates are not required. For

example, two or more AD7865s may be synchronized by using

the same external clock for all devices. In this way there is no

latency between output logic signals like EOC due to differences

in the frequency of the internal clock oscillators. Figure 10

shows how the various logic outputs are synchronized to the CLK

сигнала. The first falling edge of CLKIN must not occur until

200 ns after a conversion has been initiated (rising edge of

CONVST ), at which point BUSY will go high. The AD7865

will then convert the analog input signal on the first selected

channel (see Selecting a Conversion Sequence) at a rate deter-

mined by the CLKIN. No external events will occur until the

14th falling edge of CLKIN. The data register output address

is then reset to point to Data Register 1 and FRSTDATA goes

high. This first conversion is complete on the 15th falling edge

of the CLKIN (indicated by EOC going low) and the result

from this conversion is loaded into Data Register 1. EOC goes

high again on the 16th falling edge of CLKIN. Figure 10 shows

a RD pulse occurring when EOC is low, enabling the conversion

result in Data Register 1 onto the data bus. The next 16 pulses

of CLKIN will convert the analog input signal on the second

selected channel and so on until all selected channels have been

converted. BUSY and EOC will go low on the 15th falling edge

of the last conversion sequence and EOC will return high on the

16th falling edge.

Standby Mode Operation

The AD7865 has a Standby Mode whereby the device can be

placed in a low current consumption mode (3 µA typ).

AD7865 is placed in standby by bringing the logic input STBY

low. The AD7865 can be powered up again for normal opera-

tion by bringing STBY logic high. The output data buffers are

still operational while the AD7865 is in standby. This means the

user can still continue to access the conversion results while the

AD7865 is in standby. This feature can be used to reduce the

average power consumption in a system using low throughput

rates. To reduce the average power consumption the AD7865 can

be placed in standby at the end of each conversion sequence,

ie, when BUSY goes low and taken out of standby again prior

to the start of the next conversion sequence. The time it takes

the AD7865 to come out of standby is called the “wake-up”

время. This wake-up time will limit the maximum throughput

rate at which the AD7865 can be operated when powering down

between conversions. The AD7865 will wake up in less than

1 µs when using an external reference. When the internal refer-

ence is used, the wake-up time depends on the amount of time

the AD7865 spends in standby mode. For standby times of less

than 10 ms the AD7865 will wake up in less than 5 µs (see Fig-

ure 11). For standby times greater than this some or all of the

charge on the external reference capacitor will have leaked away

and the wake-up time will be dependent on how long it takes to

recharge. For standby times less than one second the wake-up

time will be less than 1 ms. Even if the charge has been completely

depleted the wake-up time will typically be less than 10 ms.

STANDBY TIME – s

0

0

2500

5000

7500

10000

2,5

5

WAKE-UP TIME

–

ы

Figure 11. Wake-Up Time vs. Standby Time Using the On-

Chip Reference

FIRST CONVERSION

COMPLETE

BUSY

RD

EOC

FRSTDATA

CONVST

CLK

т

18

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14

1

15 16

16

15

LAST CONVERSION

COMPLETE

Figure 10. Using an External Clock

REV. B

AD7865

–15–

When operating the AD7865 in a standby mode between con-

versions, the power savings can be significant. Например,

with a throughput rate of 10 kSPS and external reference, the

AD7865 will be powered up 11 µs out of every 100 µs (1 µs for

wake-up time and 9.6 µs to convert four channels. Therefore,

the average power consumption drops to (115 mW × 10.6%) or

12.2 mW approximately.

OFFSET AND FULL-SCALE ADJUSTMENT

In most Digital Signal Processing (DSP) applications, offset and

full-scale errors have little or no effect on system performance.

Offset error can always be eliminated in the analog domain by

ac coupling. Full-scale error effect is linear and does not cause

problems as long as the input signal is within the full dynamic

range of the ADC. Invariably, some applications will require

that the input signal span the full analog input dynamic range.

In such applications, offset and full-scale error will have to be

adjusted to zero.

Figure 13 shows a typical circuit that can be used to adjust the

offset and full-scale errors on the AD7865 (V

1

on the AD7865-1

version is shown for example purposes only). Where adjustment

is required, offset error must be adjusted before full-scale error.

This is achieved by trimming the offset of the op amp driving

the analog input of the AD7865 while the input voltage is

1/2 LSB below analog ground. The trim procedure is as follows:

apply a voltage of –610 µV (–1/2 LSB) at V

1

and adjust the op

amp offset voltage until the ADC output code flickers between

1111 1111 1111 and 0000 0000 0000.

Gain error can be adjusted at either the first code transition

(ADC negative full scale) or the last code transition (ADC posi-

tive full scale). The trim procedures for both cases are as follows.

V

1

R1

10k

R2

500

R3

10k

AGND

AD7865*

*ADDITIONAL PINS OMITTED FOR CLARITY

INPUT

RANGE = 10V

R5

10k

V

INxA

R4

10k

Figure 13. Full-Scale Adjust Circuit

Positive Full-Scale Adjust

Apply a voltage of 9.9982 V (FS/2 – 3/2 LSB) at V

1

. Adjust R2

until the ADC output code flickers between 01 1111 1111 1110

and 01 1111 1111 1111.

Negative Full-Scale Adjust

Apply a voltage of –9.9998 V (–FS + 1/2 LSB) at V

1

and adjust

R2 until the ADC output code flickers between 10 0000 0000

0000 and 10 0000 0000 0001.

An alternative scheme for adjusting full-scale error in systems

that use an external reference is to adjust the voltage at the V

REF

pin until the full-scale error for any of the channels is adjusted

out. The good full-scale matching of the channels will ensure

small full-scale errors on the other channels.

DYNAMIC SPECIFICATIONS

The AD7865 is specified and 100% tested for dynamic perfor-

mance specifications as well as traditional dc specifications such

as Integral and Differential Nonlinearity. These ac specifications

are required for such signal processing applications as phased array

sonar, adaptive filters and spectrum analysis. These applications

require information on the ADC's effect on the spectral content

of the input signal. Hence, the parameters for which the AD7865

is specified include SNR, harmonic distortion, intermodulation

distortion and peak harmonics. These terms are discussed in

more detail in the following sections.

Signal-to-Noise Ratio (SNR)

SNR is the measured signal-to-noise ratio at the output of the

ADC. The signal is the rms magnitude of the fundamental.

Noise is the rms sum of all the nonfundamental signals up to

half the sampling frequency (f

S

/2) excluding dc. SNR is depen-

dent upon the number of quantization levels used in the digitization

process; the more levels, the smaller the quantization noise.

theoretical signal to noise ratio for a sine wave input is given by

SNR = (6.02 N + 1.76) dB